general description the gd16333 is 4:32 demultiplexer, in - tended for use with gd16544, an stm-64 receiver and 1:16 demultiplexer or in dsp applications with fast adc?s. the gd16333 consists of: u four 1:8 demultiplexers u a clock generator circuit u a synchronisation circuit. the synchronisation circuit enables a parallel coupling of several devices. this is done with a master clock divider, which distributes a synchronisation signal to the parallel devices. the gd16333 is provided in a 100 pin power enhanced plastic package. the chip is designed for operation be - tween -5 e c and +85 e c (case tempera - ture). preliminary features l clock frequency to 622 mhz. l 4:32 demux obtained by four 1:8 demux. l high-speed differential inputs, cml/pecl level. l data outputs are cmos level. l 100 pin qfp (14 x 20 mm) power enhanced plastic package. l power consumption : 1 w typical. l synchronisation of parallel devices for wider bus widths. l 5 v single supply operation. applications l tele communication: ? stm-64 stm-16 ? oc-192 oc-48 l dsp ? high speed adc interface 622 mhz 4:32 demultiplexer gd16333 data sheet rev. 07 sync div.2/4/8 div. 8 clk fck fcko synco cko tstr vddc vdd vee vcs o3, o7..o31 o2, o6..o30 o1, o5..o29 o0, o4..o28 in0 in1 in2 in3 in0n in1n in2n in3n syncn clkn fckn fckon syncon
functional details synchronisation the gd16333 provides a synchronisa - tion block that allows parallel expansion of devices for wider data width. when this is required only one synchronisation block is used as a master controller, which drives the synchronisation input of all parallel demux devices. the synchronisation block provides a clock output (fcko) and a synco sig - nal (which is a 1/8 clock signal) timed by the fcko output. these signals are then daisy-chained to the clk and sync in - puts of all the demux devices. this solu - tion provides a fully synchronised parallel demultiplexer structure, where all demux data ports samples data in the same clock cycle. figure 1. gd16544: 10 gbit/s, stm-64 receiver application. the data inputs (fck, clk and sync) allow for either cml or pecl termina - tion. termination resistors must be pro - vided externally (i.e. 50 w to v dd if cml or 50 w to v dd -2 v if pecl). the fcko and synco outputs are both open drain outputs accommodating the clk and sync inputs in cml configuration. there are two ways to connect the mas - ter clock, provided at the input to the gd16333?s from the upstream device, with different timing constrains. using the clock output (fcko) from the synchroni - sation block, will give a good timing con - dition for the sync signal path, with respect to the clock. but it will put con - strains on the timing at the data inputs, since the synchronisation block will add a delay to the master clock, with respect to the data coming from the upstream device (refer to figure 1). another approach is to feed the input clock directly to the clk input of the demux?es, maintaining the data/clock relations as given by the upstream de - vice (refer to figure 2). this will however put constrains on the timing of the sync signal path. depending on actual timing of the upstream device and actual board layout, both approaches may prove use - ful. in either case, to compensate for board delays use the near-end device as clock master such that the clock propagating to the following slave devices outcompen - sates data propagating from the gd16544. figure 2. maintaining fast cloc k<-> data relations practical considerations the sync and clk control signals are differential high-speed control signals. care should be taken to design the rout - ing of these signals as transmission lines, i.e. as coplanar wave guides, or as strip lines. the signals should be routed without branches from the signal source with shortest possible distance to the first load, then onwards to the next load, and finally terminating in a resistor matching the transmission line impedance, nor - mally 50 w . the transmission line should not have any branches in order to mini - mise stub effects (reflections). data sheet rev. 07 gd16333 page 2 of 9 in0 in1 in2 in3 synco cko o31 o0 sync clk fck gd16333 in0 in1 in2 in3 synco cko o31 o0 sync clk fck gd16333 32 32 4 4 in0 in1 in2 in3 synco fcko o31 o0 sync clk fck gd16333 in0 in1 in2 in3 synco fcko o31 o0 sync clk fck gd16333 in0 in1 in2 in3 synco fcko o31 o0 sync clk fck gd16333 in0 in1 in2 in3 synco fcko o31 o0 sync clk fck gd16333 cko gd16544 4 4 4 4 16 laser ldd laser driver e.g. gd19901 gd19903 termination 32 32 32 32
pin list mnemonic: pin no.: pin type: description: in0, in0n in1, in1n in2, in2n in3, in3n 8, 9 72, 71 58, 59 23, 22 cml/pecl in 622 mhz differential data input. clk, clkn 61, 62 cml/pecl in 622 mhz differential clock input. sync, syncn 63, 64 cml/pecl in 78 mhz differential synchronization input. o0, o4, o8, o12, o16, o20, o24, o28 6, 5, 4, 3, 98, 97, 96, 95 cmos out 78 mhz demuxed in0. o1, o5, o9, o13, o17, o21, o25, o29 74, 75, 76, 77, 83, 84, 85, 86 cmos out 78 mhz demuxed in1. o2, o6, o10, o14, o18, o22, o26, o30 56, 55, 54, 53, 48, 47, 46, 45 cmos out 78 mhz demuxed in2. o3, o7, o11, o15, o19, o23, o27, o31 25, 26, 27, 28, 33, 34, 35, 36 cmos out 78 mhz demuxed in3. cko 68 cmos out 78 mhz clock output. fck, fckn 15, 16 cml/pecl in 622 mhz differential input to clock divider. fcko, fckon 19, 20 cml out 622 mhz differential clock output. synco, syncon 17, 18 cml out 78 mhz differential synchronisation output, timing identical to fcko, for synchronisation. tstr 14 sing. pecl in reset to clock divider. for normal operation, connect with 1k s to vee. only for test purpose. vcs 12 sense internal control voltage sense, leave open. vee 7, 11, 13, 24, 31, 32, 38, 37, 43, 44, 49, 50, 57, 66, 69, 73, 81, 82, 87, 88, 93, 94, 99, 100 gnd 0 v. vddc 1, 30, 39, 42, 51, 67, 80, 89, 92 pwr 5 v, power supply to cmos output drivers. vdd 10, 21, 40, 41, 60, 65, 70, 90, 91 pwr 5 v. nc 2, 29, 52, 78, 79 not connected. heat sink connect to vee data sheet rev. 07 gd16333 page 3 of 9
package pinout figure 3. package 100 pin qfp, top view data sheet rev. 07 gd16333 page 4 of 9 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 33 35 32 34 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 97 100 96 99 95 98 94 93 92 91 90 89 88 87 86 85 84 83 82 81 vddc nc nc o13 o9 o5 o1 vee in1 in1n vdd vee cko vddc vee vdd syncn sync clkn clk vdd in2n in2 vee o2 o6 o10 o14 nc vddc vee vee o18 o22 o26 o30 vee vee vddc vdd vdd vddc vee vee o31 o19 o27 vee o23 vee vddc nc o12 o8 o4 o0 vee in0 in0n vdd vee vcs vee tstr fck fckn synco syncon fcko fckon vdd in3n in3 vee o3 o7 o11 o15 nc vddc o20 vee o24 vee o28 o16 vee vee vddc vdd vdd vddc vee vee o29 o25 o21 o17 vee vee
maximum ratings these are the limits beyond which the component may be damaged. all voltages in table are referred to vee. all currents are defined positive out of the pin. symbol: characteristic: conditions: min.: typ.: max.: unit: v dd positive supply rel. to vee 06v v o max output voltage pecl -0.5 v dd +0.5 v i o max output current cml -15 0 ma i o max output current cmos data -15 15 ma i o max output current cmos cko -30 30 ma v i max input voltage pecl -0.5 v dd +0.5 v i i max input current pecl -1.0 1.0 ma t s operating temperature junction -55 +150 e c t o storage temperature -65 +175 e c thermal characteristics symbol: characteristic: conditions: min.: typ.: max.: unit: q j-c thermal resistance, junction to case 11.7 c/w q j-a thermal resistance, junction to ambient still air, horizontal mounting 42 c/w t o operating temperature case -5 85 c thermal considerations a heat-conducting slug is placed at the bottom of the package allowing heat dissipation out of the bottom of the ic package to the pcb. the heat slug can be soldered to a conducting plane (vee) on the pcb using solder paste, or a thermally conducting foil can be placed under the package. if the thermal foil method is preferred, a 0.25 mm thick foil may be used. via holes for heat transfer to the other side of the pcb should be made and a heat sink can be attached on the opposite side of the pcb if required. data sheet rev. 07 gd16333 page 5 of 9
dc characteristics all voltages in table are referred to vee. all currents are defined positive out of the pin. t case =-5 e cto85 e c. symbol: characteristic: conditions: min.: typ.: max.: unit: v dd supply voltage 4.75 5.00 5.40 v i dd supply current note 1 220 ma v cm, cml/pecl cml/pecl input common mode voltage note 2 v dd -2 v dd - 0.2 v v diff, cml/pecl cml/pecl input differential swing note 3 100 1400 mv i ih, pecl cml/pecl input hi current v ih max 100 a i il, pecl cml/pecl input lo current v il max -100 a v ipp, cml cml differential input v p-p 100 mv v opp, cml cml differential output v p-p 200 mv v oh, cmos cmos output hi voltage 4 v v ol, cmos cmos output lo voltage 0.4 v i oh, cmos cmos output hi current data 4 ma i oh, cmos cmos output hi current cko 16 ma i ol, cmos cmos output lo current data -4 ma i ol, cmos cmos output lo current cko -16 ma note 1: measured at dc, no signal on cmos outputs. note 2: v cm = vv pn + 2 note 3: v diff = vv pn - data sheet rev. 07 gd16333 page 6 of 9 v n v p
ac characteristics symbol: characteristic: conditions: min.: typ.: max.: unit: tpd,fcko delay from fck to fcko 900 ps tpd,synco delay from fck to synco 1300 ps ts,in input set-up time before clk 250 ps th,in input hold time after clk -100 ps ts,sync sync set-up time before clk -500 ps th,sync sync hold time after clk 700 ps tpd cko to output delay 3200 ps note: all timing data are based on one prototype measurement. figure 4. fast clock divider figure 5. input figure 6. output note: when sync is sampled low, after a high sample, the internal clock divider is reset, giving a low cko and data output two clk samples after sync is sampled low. figure 7. input/output relations data sheet rev. 07 gd16333 page 7 of 9 fck fcko synco t pd,fcko t pd,synco clk in sync t s,in t s,sync t h,in t h,sync cko out t pd sync input output in clk cko out d0 d0..d7 -2 d0..d7 -1 d1 d2 d3 d4 d5 d6 d7
package outline figure 8. package 100 pin qfp, power enhanced. device marking figure 9. device marking - top view data sheet rev. 07 gd16333 page 8 of 9 bottom view gd16333
ordering information to order, please specify as shown below: product name: package type: case temperature range: options: gd16333 - qfp100 100 pin qfp, edquad -5 e c..+85 e c gd16333, data sheet rev. 07 - date: 3 march 2000 the information herein is assumed to be reliable. giga assumes no responsibility for the use of this information, and all such information shall be at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. giga does not authorise or warrant any giga product for use in life support devices and/or systems. mileparken 22, dk-2740 skovlunde denmark phone : +45 7010 1062 fax : +45 7010 1063 e-mail : sales@giga.dk web site : http://www.giga.dk please check our internet web site for latest version of this data sheet. distributor: copyright ? 2000 giga a/s all rights reserved
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